EP20K100QI240-2 vs EP20K100QC240-3N 比較
詳細並排比較 EP20K100QI240-2 由 Intel 與 EP20K100QC240-3N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K100QI240-2 | EP20K100QC240-3N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Family | APEX 20K | APEX-20K |
| Series | EP20K100 | — |
| Device Type | Field Programmable Gate Array (FPGA) | FPGA |
| Typical Gates | 100,000 | — |
| Logic Elements / Cells | 4,160 | — |
| Embedded RAM Bits | 53,248 | — |
| Number of Logic Elements | 4,160 | — |
| User I/Os | 189 | — |
| Number of Dedicated Inputs | 4 | — |
| Global Clocks | 4 | — |
| Propagation Delay | 1.6 ns | — |
| Maximum Internal Frequency | 200 MHz | — |
| Core Voltage | 2.5 V | — |
| Process Technology | 0.22 µm CMOS | — |
| Package Type | 240-pin Power QFP (PQFP / BFQFP) | — |
| Pin Pitch | 1.27 mm | — |
| 工作溫度 | 0 °C to +85 °C (Commercial) | 0 C to 85 C |
| 安裝類型 | Surface Mount | Surface Mount |
| Lead Finish | Tin-Lead (SnPb) | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | unknown |
| Gate Count | — | 100000 gates |
| Logic Cells | — | 4160 cells |
| User I/O | — | 189 I/O |
| Distributed Memory | — | 53248 bits |
| Macrocells | — | 416 macrocells |
| 供應電壓 | — | 2.375 V to 2.625 V |
| Nominal Supply | — | 2.5 V |
| Maximum Frequency | — | 167 MHz |
| 封裝 | — | 240-BFQFP |
| 腳位數 | — | 240 pins |
| Fabrication Process | — | 0.15 um all-layer copper-metal process |
| Package Pitch | — | 1.27 mm |
| Package Dimensions | — | 45 mm x 45 mm |
| AEC-Q100 | — | not_qualified |