EP20K1500EBC652-1X vs EP20K200EBC652-3N 比較
詳細並排比較 EP20K1500EBC652-1X 由 Altera 與 EP20K200EBC652-3N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K1500EBC652-1X - APEX 20KE 1.5M Gates FPGA | Altera | BGA-652
EP20K1500EBC652-1X Obsolete規格比較
| 參數 | EP20K1500EBC652-1X | EP20K200EBC652-3N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KE | — |
| Logic Elements / Cells | 51840 | 8,320 |
| System Gates | 1.5 M | 200,000 |
| Macros | 3456 | — |
| Total RAM Bits | 442368 | — |
| User I/O | 488 | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Propagation Delay | 1.84 ns | 2.33 ns |
| Internal Frequency | 160 MHz (per digchip) / 400 MHz (per fpgakey) | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| 工作溫度 | 0 °C to +85 °C (commercial) | — |
| 封裝 | 652-ball BGA (FCBGA / PBGA652) | 652-ball BGA |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Compliant |
| Configuration Method | JTAG / SRAM | — |
| Architecture | MultiCore (LUT + product-term) | — |
| Series | — | APEX 20KE (APEX-20KE®) |
| Device Family | — | EP20K200 |
| Logic Array Blocks (LABs) | — | 832 |
| Macrocells | — | 832 |
| Embedded RAM | — | 106,496 bits |
| User I/Os (DigiKey listing) | — | 376 |
| User I/Os (digchip listing) | — | 277 |
| Internal Frequency (max) | — | 189 MHz |
| Core Supply Voltage | — | 1.71 V to 1.89 V (nominal 1.8 V) |
| I/O Supply (LVDS-capable) | — | LVDS, 2.5 V referenced (per source variant) |
| Operating Temperature (TJ) | — | 0 °C to 85 °C (commercial) |
| Speed Grade | — | -3 (slowest in APEX 20KE family) |
| Configuration | — | JTAG (IEEE 1149.1), Passive Serial |