EP20K200CQ208C8N vs EP20K200CQ208C9 比較

詳細並排比較 EP20K200CQ208C8N 由 Altera 與 EP20K200CQ208C9 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K200CQ208C8N EP20K200CQ208C8N - APEX 20KC FPGA 1.8V | Altera

EP20K200CQ208C8N - APEX 20KC FPGA 1.8V | Altera

EP20K200CQ208C8N Obsolete

規格比較

參數 EP20K200CQ208C8N EP20K200CQ208C9
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Family APEX 20KC —
Product Type FPGA / Loadable PLD —
Logic Elements / Cells 8320 8320
Typical Gates 200K gates —
Total RAM Bits 106496 106496
User I/O Pins 144 —
Dedicated Inputs 4 —
Package Description 208-Pin PQFP/BFQFP —
Number of Terminals 208 —
Terminal Form Gull Wing —
Package Shape Square —
Core Supply Voltage 1.8 V 1.8V
Process Technology 0.15 um —
Maximum Internal Frequency 301.21 MHz 250 MHz
I/O Standard Support [DATA_NEEDED: I/O standard support] —
Embedded System Block Count [DATA_NEEDED: ESB count] —
工作溫度範圍 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: Operating Temperature Range]
Configuration Scheme [DATA_NEEDED: configuration scheme] —
RoHS / Lead-Free Status [DATA_NEEDED: RoHS status] —
安裝類型 Surface Mount Surface Mount
Family — APEX-20KC
Total Gates — 200K typical
Technology — 0.15 um CMOS
Voltage - Supply Range — 1.71V ~ 1.89V
封裝 / 外殼 — 208-BFQFP
Supplier Device Package — 208-PQFP (28x28)
腳位數 — 208
Device Type — LOADABLE PLD, CMOS
Internal Propagation Delay — 2 ns
Core Architecture — SRAM-based FPGA
Number of I/O — [DATA_NEEDED: Number of I/O]
RoHS 狀態 — [DATA_NEEDED: RoHS Status]

資料表與資源

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