EP20K200CQ240C7 vs EP20K200CQ240C8N 比較

詳細並排比較 EP20K200CQ240C7 由 Altera 與 EP20K200CQ240C8N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K200CQ240C7 EP20K200CQ240C7 - 8320 LE APEX-20KC FPGA | Altera

EP20K200CQ240C7 - 8320 LE APEX-20KC FPGA | Altera

EP20K200CQ240C7 Obsolete

規格比較

參數 EP20K200CQ240C7 EP20K200CQ240C8N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Product Type Field Programmable Gate Array (FPGA) Loadable Programmable Logic Device (PLD / FPGA)
Series APEX-20KC EP20K200
Number of Logic Elements / Cells 8320 —
Total RAM Bits 106496 —
Number of User I/Os 168 —
封裝 / 外殼 240-BFQFP 240-Pin PQFP (CQ240)
Supplier Description IC FPGA 168 I/O 240QFP —
安裝類型 Surface Mount Surface Mount
Speed Grade [DATA_NEEDED: C7 maximum clock/timing data] 8 (from C8N suffix)
Core Supply Voltage [DATA_NEEDED: APEX-20KC core voltage] 1.8 V
I/O Supply Voltage [DATA_NEEDED: APEX-20KC I/O voltage range] —
工作溫度範圍 [DATA_NEEDED: commercial C grade range] —
最大時脈頻率 [DATA_NEEDED: C7 speed-grade fMAX] 301.21 MHz
Configuration Voltage [DATA_NEEDED: configuration I/O voltage] —
RoHS 狀態 [DATA_NEEDED: manufacturer compliance statement] —
REACH Status [DATA_NEEDED: manufacturer compliance statement] —
Manufacturer — Altera Corporation
Family — APEX 20KC
Total Gates (typical) — 200K gates
Logic Elements / Cells — 8,320 cells
Dedicated I/O Lines — 168
Input Terminals — 164
Dedicated I/O Pins — 160
Process Technology — 0.15 um
Temperature Grade — Commercial (C) [DATA_NEEDED: exact operating temperature range in °C]
Configuration Device Support — Altera enhanced configuration device (from EP20K200 datasheet description)
I/O Voltage Support — [DATA_NEEDED: supported I/O bank standards and voltage ranges]
Embedded RAM Bits — [DATA_NEEDED: total memory bits for EP20K200]
RoHS / Lead-Free Status — [DATA_NEEDED: RoHS status; N suffix normally used for lead-free but not stated in fetched data]

資料表與資源

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