EP20K200FC484-2X vs EP20K200FC484-1XV 比較
詳細並排比較 EP20K200FC484-2X 由 Altera 與 EP20K200FC484-1XV 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K200FC484-2X - 200K Gates APEX 20K FPGA, 484-FBGA | Intel / Altera
EP20K200FC484-2X Obsolete規格比較
| 參數 | EP20K200FC484-2X | EP20K200FC484-1XV |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K |
| Series | EP20K200 | APEX-20K® |
| Device Type | FPGA (Field Programmable Gate Array) | Field Programmable Gate Array (FPGA) |
| Maximum Logic Elements | 8,320 cells | 8,320 |
| Typical System Gates | 200,000 | — |
| Embedded Memory (EAB) | 106,496 bits | — |
| Maximum User I/O | 382 | — |
| Number of Logic Elements | 8,320 | — |
| Propagation Delay | 3.0 ns | — |
| Maximum Internal Frequency | 200 MHz | 250 MHz |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| 封裝 | 484-pin FBGA (FineLine BGA), 1.0 mm pitch | 484-FBGA (FC484), 23 mm x 23 mm, 1.27 mm pitch |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | 0 °C to 85 °C (commercial) | Industrial / military (per variant) |
| Speed Grade | -2 (with LVDS support, "X" suffix) | -1 (with XV extended/reprocurement suffix) |
| Programmable I/O Standards | 1.8 V, 2.5 V, 3.3 V, LVTTL, LVCMOS, LVDS | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: exact RoHS statement] |
| Maximum System Gates | — | 200,000 (typical) |
| Maximum User I/O Pins | — | 382 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 106,496 |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |