EP20K400CB652C9N vs EP20K400CB652I8N 比較
詳細並排比較 EP20K400CB652C9N 由 Intel 與 EP20K400CB652I8N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400CB652C9N | EP20K400CB652I8N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | — |
| Device Type | Programmable Logic Device (SOPC FPGA) | — |
| Architecture | MultiCore (LUT logic + Embedded System Blocks) | — |
| System Gates | 400,000 | 400,000 |
| Logic Elements | 16,640 | 16,640 |
| Maximum User I/Os | 502 | — |
| Total Memory Bits | 212,992 (per chip) | — |
| Maximum Internal Frequency | 250 MHz | — |
| Propagation Delay | 2.0 ns | — |
| Logic Family | CMOS | — |
| Core Process Technology | 0.15 µm all-layer copper CMOS | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V | — |
| 工作溫度範圍 | 0 °C to +85 °C (Commercial) | — |
| 封裝 | BGA-652 (Plastic Ball Grid Array, 652 balls) | 652-pin BGA |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Interface | IEEE 1149.1 JTAG, serial passive parallel async | JTAG / Passive Serial |
| RoHS 狀態 | Unknown (legacy Altera part - verify with distributor) | unknown |
| Macrocells | — | 1664 |
| Number of User I/O | — | 488 |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Number of Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Number of PLLs | — | 4 |
| Embedded Memory (Max) | — | [DATA_NEEDED: total embedded memory bits] |
| Maximum Operating Frequency | — | 301.21 MHz |
| Process Technology | — | 0.15 µm CMOS |
| Core Voltage | — | 1.8 V |
| I/O Voltage (MultiVolt) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Operating Temperature (Industrial) | — | -40°C to +100°C |
| Speed Grade | — | 8 |
| Lead-Free | — | unknown |
| Design Tool | — | Altera Quartus II (APEX 20KC support) |