EP20K400CF672C-8 vs EP20K400CF672C7 比較
詳細並排比較 EP20K400CF672C-8 由 Altera 與 EP20K400CF672C7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400CF672C-8 | EP20K400CF672C7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KC (MultiCore™) |
| Logic Elements | 16,640 | — |
| Typical Gates | 400,000 | — |
| Macros | 1,664 | — |
| Maximum User I/O | 488 | 488 |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | 8 |
| Package Type | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) | — |
| Core Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO options] | — |
| Pin-to-Pin Delay (tPD) | 1.78 ns (speed grade -8) | — |
| Speed Grade | -8 | -7 |
| Temperature Grade (C) | Commercial, 0 °C to 85 °C | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 µm CMOS |
| Embedded Memory Type | ESB (RAM / ROM / CAM) | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Non-compliant (legacy product) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Series | — | APEX-20KC |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Embedded Memory (RAM bits) | — | 212,992 |
| 封裝 | — | 672-BBGA (FC-FBGA, FineLine BGA) |
| 腳位數 | — | 672 |
| Core Voltage | — | 1.8 V |
| 供應電壓 | — | 2.5 V (I/O reference) |
| Propagation Delay (tPD) | — | 2.5 ns |
| Maximum Internal Frequency | — | 375.94 MHz |
| 工作溫度 | — | 0 °C to +85 °C (Commercial, C-grade) |
| PLL Count | — | 4 |
| Lead-Free | — | Contains lead (legacy BGA finish) |