EP20K400CF672C7N vs EP20K400CF672C7ES 比較
詳細並排比較 EP20K400CF672C7N 由 Altera 與 EP20K400CF672C7ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400CF672C7N | EP20K400CF672C7ES |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Maximum System Gates | 1,052,000 | — |
| Typical Gates | 400,000 | — |
| Logic Elements (LEs) | 16,640 | — |
| Embedded Memory | 488 Kbits | — |
| Maximum User I/O | 488 | 488 |
| User I/O (per catalog) | 480 / 502 (per source) | — |
| 封裝 | 672-ball FineLine BGA (FC-FBGA / BBGA) | — |
| Process Technology | 0.18-micron CMOS, all-layer copper interconnect | 0.18 um CMOS |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 3.3 V / 2.5 V banked | — |
| Propagation Delay | 2.5 ns (catalog) / 1.48 ns (some catalog) | 1.4 ns |
| Maximum Frequency | 375.94 MHz (internal) | — |
| 工作溫度 | 0 C to 85 C (Commercial) | 0C to +85C (commercial) |
| 安裝類型 | Surface Mount (BGA) | Surface Mount |
| MSL 等級 | 3 (per JEDEC J-STD-020) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not in provided data] | [DATA_NEEDED: RoHS compliance] |
| Configuration Modes | PS, PPS, JTAG | — |
| Series | — | EP20K400 |
| Device Type | — | Loadable PLD / FPGA |
| Logic Elements (Cells) | — | 16,640 |
| System Gates | — | 400,000 |
| Embedded Memory (Bits) | — | 212,992 |
| Total RAM Bits | — | 212,992 |
| I/O Lines | — | 484 |
| Input Lines | — | 488 |
| Number of PLLs | — | 4 |
| Maximum Internal Clock Frequency | — | 375.94 MHz |
| Core Voltage | — | 1.8 V |
| MultiVolt I/O | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | — | C7 (commercial, -7) |
| Package Type | — | 672-ball FineLine BGA |
| Package Code | — | FC-FBGA-B672 |
| Ball Pitch | — | 1.000 mm |