EP20K400CF672C8ES vs EP20K400CF672C7ES 比較
詳細並排比較 EP20K400CF672C8ES 由 Altera 與 EP20K400CF672C7ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400CF672C8ES | EP20K400CF672C7ES |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | EP20K400 |
| Logic Cells / Macros | 16,640 | — |
| System Gates (typical) | 400,000 | — |
| System Gates (maximum) | 212,992 [DATA_NEEDED: confirm datasheet interpretation] | — |
| Maximum User I/O | 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value] | 488 |
| Bidirectional I/O | 484 | — |
| Propagation Delay | 2.5 ns | 1.4 ns |
| Maximum Internal Frequency | 301.21 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.18 um CMOS |
| Nominal Supply Voltage | 1.8 V | — |
| Supply Voltage Range | 1.71 V to 1.89 V | — |
| 工作溫度 | 0°C to 85°C (Commercial) | 0C to +85C (commercial) |
| 封裝 | 672-BGA FineLine (FC-FBGA / S-PBGA-B672) | — |
| Logic Family | CMOS | — |
| Architecture | MultiCore™ (LUT + Embedded System Block) | — |
| Programming Method | JTAG / in-system via configuration memory | — |
| RoHS 狀態 | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS compliance] |
| Device Type | — | Loadable PLD / FPGA |
| Logic Elements (Cells) | — | 16,640 |
| System Gates | — | 400,000 |
| Embedded Memory (Bits) | — | 212,992 |
| Total RAM Bits | — | 212,992 |
| I/O Lines | — | 484 |
| Input Lines | — | 488 |
| Number of PLLs | — | 4 |
| Maximum Internal Clock Frequency | — | 375.94 MHz |
| Core Voltage | — | 1.8 V |
| MultiVolt I/O | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | — | C7 (commercial, -7) |
| Package Type | — | 672-ball FineLine BGA |
| Package Code | — | FC-FBGA-B672 |
| Ball Pitch | — | 1.000 mm |
| 安裝類型 | — | Surface Mount |