EP20K400CF672C9ES vs EP20K400CF672C8ES 比較

詳細並排比較 EP20K400CF672C9ES 由 Altera 與 EP20K400CF672C8ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K400CF672C9ES EP20K400CF672C8ES
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20KC APEX 20KC
Series APEX-20KC EP20K400
Logic Elements / Cells 16640 —
Gate Count 400000 —
Number of Gates 400 K —
Voltage - Supply (Core) 1.8 V —
Maximum Internal Frequency 250 MHz 301.21 MHz
Total RAM Bits 488 kbit —
Process Technology 0.18 µm CMOS 0.15 µm CMOS
Number of I/O 488 —
封裝 / 外殼 672-BBGA, FCBGA —
安裝類型 Surface Mount —
工作溫度 0 °C to +85 °C (commercial) 0°C to 85°C (Commercial)
Speed Grade 9 —
MultiVolt I/O Support 1.8 V / 2.5 V / 3.3 V —
In-System Programmability Yes (JTAG) —
RoHS 狀態 Unknown [DATA_NEEDED: not stated in verified data]
Lead-Free Unknown —
Logic Cells / Macros — 16,640
System Gates (typical) — 400,000
System Gates (maximum) — 212,992 [DATA_NEEDED: confirm datasheet interpretation]
Maximum User I/O — 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value]
Bidirectional I/O — 484
Propagation Delay — 2.5 ns
Nominal Supply Voltage — 1.8 V
Supply Voltage Range — 1.71 V to 1.89 V
封裝 — 672-BGA FineLine (FC-FBGA / S-PBGA-B672)
Logic Family — CMOS
Architecture — MultiCore™ (LUT + Embedded System Block)
Programming Method — JTAG / in-system via configuration memory

資料表與資源

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