EP20K400FI672-3V vs EP20K400FI672-3X 比較
詳細並排比較 EP20K400FI672-3V 由 Intel 與 EP20K400FI672-3X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K400FI672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera/Intel
EP20K400FI672-3X ⚠ 最後購買機會規格比較
| 參數 | EP20K400FI672-3V | EP20K400FI672-3X |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | APEX 20K (EP20K400) | APEX 20K |
| Logic Elements | 16,640 | — |
| Maximum Gates | 400,000 | — |
| Typical Gates | [DATA_NEEDED: typical gates value] | — |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 6 | — |
| Total User I/O + Dedicated Inputs | 496 + 6 (variant dependent) | — |
| 最大時脈頻率 | 714.2 MHz | — |
| Speed Grade | -3 (faster) | -3 (high-performance tier) |
| Core Voltage (VCCINT) | 2.5 V nominal (2.375 V to 2.625 V) | — |
| Process Technology | 0.18 µm CMOS, 4 metal layers | — |
| 封裝 | 672-ball FineLine BGA (BBGA), 1.0 mm pitch | 672-ball Fine-Pitch BGA (S-PBGA-B672) |
| 安裝類型 | Surface Mount | Surface Mount |
| Programmable via JTAG | Yes (IEEE 1149.1) | — |
| Supported I/O Standards | LVCMOS, LVTTL, SSTL, GTL+, HSTL | — |
| Configuration Modes | JTAG, passive serial, passive parallel | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (per Intel/Altera product page) |
| 工作溫度 | -40 °C to +85 °C (industrial) | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Device Series | — | EP20K400 |
| Maximum System Gates | — | 400,000 |
| Maximum Logic Elements | — | [DATA_NEEDED: exact LE count for EP20K400] |
| Terminal Pitch | — | 1.000 mm |
| Nominal Core Voltage (VCCINT) | — | 2.5 V |
| VCCINT Range | — | 2.375 V to 2.625 V |
| Typical Propagation Delay | — | 3.6 ns |
| Maximum Internal Clock Frequency | — | 833 MHz |
| Technology | — | CMOS SRAM configuration cell |
| Temperature Grade (X suffix) | — | Industrial / extended |
| 濕度敏感等級 (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 C |