EP20K400GC655-2N vs EP20K400GC655-1X 比較
詳細並排比較 EP20K400GC655-2N 由 Altera 與 EP20K400GC655-1X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GC655-2N | EP20K400GC655-1X |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Number of Logic Elements | 16640 | — |
| Number of Logic Cells | 16640 | — |
| Total System Gates | 400000 | — |
| Total RAM Bits | 212992 | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 2.5 V (LVDS-capable) | — |
| Process Technology | 0.22 µm CMOS | 0.22 um |
| Maximum Operating Frequency | 200 MHz | — |
| Propagation Delay (Tpd) | 3.1 ns | — |
| 封裝 / 外殼 | 655-BCPGA (Ceramic Pin Grid Array) | — |
| Supplier Device Package | 655-CPGA, 62.48 x 62.48 mm | — |
| 工作溫度 | Industrial (per Altera part-number -N suffix) | — |
| 安裝類型 | Through-Hole (CPGA, socket-compatible) | — |
| LVDS Support | Yes | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Configuration Method | JTAG / Passive Serial | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Product Family | — | Altera APEX 20K |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Technology | — | CMOS |
| Gate Count | — | 400K gates |
| Logic Elements | — | 16640 cells |
| Maximum System Frequency | — | 250 MHz |
| Propagation Delay | — | 2.5 ns |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 2.5 V / 3.3 V |
| Number of User I/O | — | 496 |
| Number of Dedicated Inputs | — | 6 |
| Number of Terminals | — | 655 |
| Package Type | — | CPGA-655 (Ceramic Pin Grid Array) |
| Package Body Material | — | Ceramic |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| Embedded RAM Bits | — | [DATA_NEEDED: embedded RAM bits] |