EP20K400GC655-2X vs EP20K400GC655-1V 比較

詳細並排比較 EP20K400GC655-2X 由 Altera 與 EP20K400GC655-1V 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K400GC655-2X EP20K400GC655-1V
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20K APEX 20KE
Series APEX-20KC® —
Logic Elements / Cells 16640 —
System Gates 400000 —
Total RAM Bits 212992 —
Number of I/O 496 —
Number of Dedicated Inputs 6 —
Number of LABs/CLBs [DATA_NEEDED: number of Logic Array Blocks] —
Number of EABs [DATA_NEEDED: number of Embedded Array Blocks] —
Maximum Operating Frequency 200 MHz —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage 2.5 V —
I/O Supply Voltage (MultiVolt) 2.5 V / 3.3 V / 5 V —
Package Type 655-BCPGA (SPGA655) —
Package Body Material CERAMIC, metal-sealed cofired grid array —
Package Dimensions 47 x 47 mm —
Peak Reflow Temperature 220 °C 220 °C
安裝類型 Through-hole (CPGA) —
Programmability In-system, JTAG (IEEE 1149.1) —
工作溫度 [DATA_NEEDED: temperature grade] —
RoHS 狀態 unknown —
Logic Elements — 16,640
Typical Gate Count — 400,000 gates
Embedded Memory — 212,992 bits
Maximum User I/O — 496
Dedicated Inputs — 6
封裝 — CBGA-655 (Ceramic Ball Grid Array)
Total Terminals — 655
Supply Voltage (Core) — 2.375 V to 2.625 V (nominal 2.5 V)
Propagation Delay — 2.5 ns
Maximum Internal Frequency — 250 MHz (-1V speed grade)
LVDS Support — Yes
Moisture Sensitivity Level — MSL 1
Qualification — Not Qualified
Programming Interface — IEEE 1532 / JTAG

資料表與資源

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