EP20K400GC655-2X vs EP20K400GC655-2V 比較
詳細並排比較 EP20K400GC655-2X 由 Altera 與 EP20K400GC655-2V 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GC655-2X | EP20K400GC655-2V |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | APEX 20K | APEX 20KC (1.8 V, LVDS) |
| Series | APEX-20KC® | APEX-20KC |
| Logic Elements / Cells | 16640 | — |
| System Gates | 400000 | ~400,000 (typical marketing figure) |
| Total RAM Bits | 212992 | 212,992 |
| Number of I/O | 496 | [DATA_NEEDED: I/O count] |
| Number of Dedicated Inputs | 6 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | — |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Maximum Operating Frequency | 200 MHz | — |
| Process Technology | 0.22 µm CMOS | CMOS, 0.18 um |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | — |
| Package Type | 655-BCPGA (SPGA655) | Ceramic Pin Grid Array, through-hole |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | — |
| Package Dimensions | 47 x 47 mm | — |
| Peak Reflow Temperature | 220 °C | — |
| 安裝類型 | Through-hole (CPGA) | Through-hole (CPGA) |
| Programmability | In-system, JTAG (IEEE 1149.1) | — |
| 工作溫度 | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: temperature grade] |
| RoHS 狀態 | unknown | unknown |
| Logic Elements | — | 16,640 |
| Core Voltage (VCCINT) | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| Propagation Delay | — | 3.000 ns |
| LVDS Support | — | Yes |
| 封裝 | — | 655-CPGA (62.48 x 62.48 mm) |
| Speed Grade | — | -2 |
| Lead-Free | — | unknown |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |