EP20K400GI655-2 vs EP20K400GC655-2V 比較
詳細並排比較 EP20K400GI655-2 由 Altera 與 EP20K400GC655-2V 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-2 | EP20K400GC655-2V |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | APEX-20KC |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | — |
| Dedicated Inputs | 6 | — |
| Number of Terminals | 655 | — |
| 封裝 | SPGA-655 (47 mm x 47 mm) | 655-CPGA (62.48 x 62.48 mm) |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | 3.000 ns |
| Technology | CMOS SRAM | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: temperature grade] |
| 安裝類型 | Through-Hole / Socket | Through-hole (CPGA) |
| Moisture Sensitivity Level | 1 (per Altera family) | — |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| 生命週期狀態 | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20KC (1.8 V, LVDS) |
| Logic Elements | — | 16,640 |
| Total RAM Bits | — | 212,992 |
| System Gates | — | ~400,000 (typical marketing figure) |
| Number of I/O | — | [DATA_NEEDED: I/O count] |
| Core Voltage (VCCINT) | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| Process Technology | — | CMOS, 0.18 um |
| LVDS Support | — | Yes |
| Package Type | — | Ceramic Pin Grid Array, through-hole |
| Speed Grade | — | -2 |
| Lead-Free | — | unknown |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |