EP20K400GI655-3X vs EP20K400GI655-1X 比較
詳細並排比較 EP20K400GI655-3X 由 Intel 與 EP20K400GI655-1X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X Obsolete規格比較
| 參數 | EP20K400GI655-3X | EP20K400GI655-1X |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Unknown | Obsolete |
| Product Type | Field Programmable Gate Array | — |
| Device Family | APEX 20K | — |
| Logic Elements/Cells | 16,640 | — |
| Technology | CMOS | — |
| Terminal Count | 655 | — |
| Package Type | SPGA | Ceramic Pin Grid Array (CPGA) |
| Package Designation | SPGA655 | — |
| Package Dimensions | 47 mm x 47 mm | — |
| Power Supply | 2.5 V | — |
| Power Supply Option | 2.5/3.3 V | — |
| 安裝類型 | [DATA_NEEDED: mounting type] | Through-Hole (PGA) |
| 工作溫度 | [DATA_NEEDED: operating temperature] | -40 C to +85 C (industrial) |
| I/O Count | [DATA_NEEDED: I/O count] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory capacity] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| RoHS 狀態 | unknown | Compliant |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Device | — | EP20K400 |
| Logic Elements | — | 16640 |
| Number of Terminals | — | 655 |
| User I/O Lines | — | 502 |
| Dedicated Inputs | — | 4 |
| Package Code (JESD-30) | — | S-CPGA-P655 |
| Package Equivalence Code | — | SPGA655,47X47 |
| Package Body Material | — | CERAMIC (metal-sealed co-fired) |
| Speed Grade | — | -1 |
| Propagation Delay | — | 2.5 ns (typical for -1 grade) |
| Process Technology | — | CMOS, SRAM-based configuration |
| 濕度敏感等級 (MSL) | — | 1 |
| Peak Reflow Temperature | — | 220 C |