EP20K600CB652C8N vs EP20K600CB652C7E5 比較

詳細並排比較 EP20K600CB652C8N 由 Altera 與 EP20K600CB652C7E5 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600CB652C8N EP20K600CB652C7E5
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20KC APEX 20KC
Device Type Loadable PLD / FPGA —
System Gates 600,000 —
Logic Elements 24,320 cells —
Embedded Memory 311,296 bits —
User I/O Pins 488 —
Dedicated Inputs 4 —
Outputs 480 —
Propagation Delay (typ.) 1.48 ns —
Pin-to-Pin Timing 1.78 ns —
Internal Frequency (typ.) 301.21 MHz —
Core Supply Voltage 1.8 V nominal (1.71 V to 1.89 V) —
Process Technology 0.18 µm all-layer copper-metal 0.15 um CMOS
Speed Grade C8 7 (-1 speed bin equivalent, E5 suffix)
工作溫度 0 °C to 85 °C (commercial) 0C to +85C (commercial, suffix C7)
封裝 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch 652-ball FineLine BGA
安裝類型 Surface Mount (BGA) —
Architecture MultiCore LUT + Embedded System Blocks (ESB) —
Pin-Compatible With APEX 20KE family —
RoHS 狀態 unknown [DATA_NEEDED: RoHS compliance status]
Typical Gate Count — 600K gates
Logic Elements / Macros — 24,320
Maximum User I/O — 488
Embedded Memory (EAB bits) — 311,296 bits
Core Voltage — 1.8 V
PLL Count — 4
Supported I/O Standards — LVTTL, LVCMOS, PCI, SSTL, HSTL
Configuration Scheme — Passive Serial / JTAG / EPC16 / EPC8
生命週期狀態 — Obsolete - last time buy has passed

資料表與資源

瀏覽所有產品 建立 BOM 索取報價