EP20K600CB652C9 vs EP20K600CB652C8N 比較
詳細並排比較 EP20K600CB652C9 由 Altera 與 EP20K600CB652C8N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CB652C9 | EP20K600CB652C8N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 24,320 | — |
| Number of LABs / CLBs | 2,432 | — |
| System Gates | 1,537,000 | 600,000 |
| Total RAM Bits | 311,296 | — |
| User I/O | 488 | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| 供應電壓 | 1.71 V to 1.89 V | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.18 µm all-layer copper-metal |
| Internal Datapath Frequency | up to 250 MHz | — |
| Propagation Delay (typ.) | 1.48 ns | 1.48 ns |
| 工作溫度 | 0 °C to 85 °C (commercial) | 0 °C to 85 °C (commercial) |
| 封裝 | 652-BGA (45 × 45 mm, 1.27 mm pitch) | 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Configuration | JTAG IEEE 1149.1 / serial / EPC2-compatible | — |
| RoHS 狀態 | Compliant (per Altera product page) | unknown |
| Product Status | Obsolete (per distributor listings) | — |
| Device Type | — | Loadable PLD / FPGA |
| Logic Elements | — | 24,320 cells |
| Embedded Memory | — | 311,296 bits |
| User I/O Pins | — | 488 |
| Dedicated Inputs | — | 4 |
| Outputs | — | 480 |
| Pin-to-Pin Timing | — | 1.78 ns |
| Internal Frequency (typ.) | — | 301.21 MHz |
| Core Supply Voltage | — | 1.8 V nominal (1.71 V to 1.89 V) |
| Speed Grade | — | C8 |
| Architecture | — | MultiCore LUT + Embedded System Blocks (ESB) |
| Pin-Compatible With | — | APEX 20KE family |