EP20K600CB652I8 vs EP20K600CB652C9N 比較

詳細並排比較 EP20K600CB652I8 由 Intel 與 EP20K600CB652C9N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600CB652I8 EP20K600CB652C9N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20KC APEX 20KC
Series EP20K600 —
System Gates 600,000 —
Logic Elements / Cells 24,320 —
Maximum Operating Frequency 301.21 MHz —
Propagation Delay (tpd) 1.78 ns (CMOS) —
Process Technology 0.15 µm CMOS 0.15 micron all-layer copper CMOS
Core Supply Voltage (VCCINT) 1.8 V nominal (1.71 V to 1.89 V) —
工作溫度 -40 °C to +85 °C (Industrial) 0 C to 85 C (commercial)
封裝 652-ball FineLine BGA (S-PBGA-B652) BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch)
Package Code BGA, square —
Ball Pitch 1.27 mm —
Package Body Size 45 mm × 45 mm —
User I/O Lines 488 —
Dedicated Clock Inputs 4 —
Programming Interface IEEE 1149.1 JTAG (in-system) —
安裝類型 Surface Mount Surface Mount (BGA)
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs status]
Device Type — Loadable PLD (FPGA)
Typical Gates — 600,000
Logic Elements — 24,320
Maximum User I/O — 488
Core Supply Voltage — 1.8 V
Speed Grade — C9 (~1.48 ns propagation delay)
Architecture — MultiCore LUT + embedded system memory (ESB)
On-chip Memory — Embedded system memory blocks (dual-port RAM, FIFO)
Configuration Interface — JTAG (IEEE 1149.1) and serial/PROM configuration
Pin/Pin Compatibility — Pin-compatible with APEX 20KE devices of same package
Toolchain — Altera/Intel Quartus II (legacy APEX support)
MSL 等級 — [DATA_NEEDED: MSL level]

資料表與資源

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