EP20K600CEF672C7 vs EP20K600CB672C7 比較
詳細並排比較 EP20K600CEF672C7 由 Intel 與 EP20K600CB672C7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CEF672C7 | EP20K600CB672C7 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Intel (formerly Altera) | — |
| Series | APEX 20KC | — |
| Family | APEX 20KC (Enhanced Configuration) | APEX 20KC |
| Device Type | FPGA / Loadable PLD | FPGA / Programmable Logic Device (PLD) |
| Logic Elements / Cells | 24,320 | — |
| Gate Count (typical) | 600,000 gates | — |
| Maximum Operating Frequency | 375.94 MHz | — |
| Propagation Delay | 1.48 ns (typ) | 1.48 ns |
| User I/Os | 488 | 488 |
| Core Supply Voltage | 1.8 V | — |
| Process Technology | 0.15 µm CMOS, all-layer copper | 0.15 µm all-layer copper-metal CMOS |
| 封裝 | 672-ball FineLine BGA (FC-FBGA) | 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch) |
| Package Code | BGA-652, 45 x 45 mm, 1.27 mm pitch | — |
| 工作溫度 | 0 °C to +85 °C (commercial) | 0 °C to 85 °C (commercial) |
| Configuration | SRAM-based, serial or parallel (EPC) | — |
| Embedded Memory | EAB blocks (dual-port RAM with byte enables) | 311 kbits (EAB-based) |
| LVDS Support | True-LVDS channels integrated | — |
| MultiVolt I/O | 1.8 V, 2.5 V, 3.3 V interfaces | — |
| External Memory Interface | DDR SDRAM, QDR SRAM | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| Typical Gates | — | 600,000 |
| Maximum System Gates | — | 1,053,840 |
| Logic Elements | — | 30,960 (typical) |
| Speed Grade | — | C7 (commercial, 0 °C to 85 °C) |
| Core Voltage | — | 2.5 V |
| I/O Voltage Support | — | 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O) |
| Number of PLLs | — | 4 |
| Dual-Port RAM | — | Yes (4.5 ns access) |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT |
| Configuration Method | — | EPC configuration devices / JTAG / passive serial |