EP20K600CEF672C7 vs EP20K600CF672C7ES 比較
詳細並排比較 EP20K600CEF672C7 由 Intel 與 EP20K600CF672C7ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CEF672C7 | EP20K600CF672C7ES |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | APEX 20KC | APEX 20KC |
| Family | APEX 20KC (Enhanced Configuration) | APEX 20K |
| Device Type | FPGA / Loadable PLD | — |
| Logic Elements / Cells | 24,320 | 24320 |
| Gate Count (typical) | 600,000 gates | — |
| Maximum Operating Frequency | 375.94 MHz | 375.94 MHz (per FPGAkey listing) |
| Propagation Delay | 1.48 ns (typ) | 1.6 ns |
| User I/Os | 488 | — |
| Core Supply Voltage | 1.8 V | — |
| Process Technology | 0.15 µm CMOS, all-layer copper | 0.15 µm CMOS |
| 封裝 | 672-ball FineLine BGA (FC-FBGA) | — |
| Package Code | BGA-652, 45 x 45 mm, 1.27 mm pitch | — |
| 工作溫度 | 0 °C to +85 °C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Configuration | SRAM-based, serial or parallel (EPC) | — |
| Embedded Memory | EAB blocks (dual-port RAM with byte enables) | — |
| LVDS Support | True-LVDS channels integrated | — |
| MultiVolt I/O | 1.8 V, 2.5 V, 3.3 V interfaces | — |
| External Memory Interface | DDR SDRAM, QDR SRAM | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| System Gates | — | 600000 |
| Maximum User I/O | — | 504 |
| Maximum Input Lines | — | 508 |
| Number of Macrocells | — | 504 |
| Internal Reference Clock | — | 1666.6 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| Package Type | — | FC-FBGA |
| Pin / Ball Count | — | 672 |
| Grade Suffix | — | ES (engineering sample / extended screening) |
| 安裝類型 | — | Surface Mount (BGA) |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Configuration Memory | — | SRAM-based (volatile) |