EP20K600CF672I8 vs EP20K600CF672I8N 比較
詳細並排比較 EP20K600CF672I8 由 Altera 與 EP20K600CF672I8N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CF672I8 | EP20K600CF672I8N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Device Type | SPLD / FPGA | SPLD / PLD (FPGA-class) |
| Logic Elements / Cells | 24,320 | 24,320 |
| Macros (Logic Cells) | 2432 | — |
| Typical Gate Count | 600,000 gates | — |
| Embedded Memory | 311,296 bits | — |
| User I/Os | 488 to 508 | — |
| 腳位數 | 652 (functional) / 672 (BGA balls) | — |
| Propagation Delay (typical) | 1.48 ns | — |
| Internal Frequency (max) | [DATA_NEEDED: max internal frequency in MHz] | — |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Process Technology | 0.15 µm all-layer copper | 0.15-um all-layer copper-metal |
| 工作溫度 | 0 °C to +85 °C (Industrial) | 0C to 85C (Industrial) |
| Package Type | 672-ball BGA, 45 x 45 mm, 1.27 mm pitch | FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | Compliant per legacy product records | [DATA_NEEDED: RoHS compliance status] |
| Configuration Interface | JTAG / Passive Serial | — |
| Design Tool | Quartus II (legacy MAX+PLUS II) | — |
| Device Family | — | APEX 20KC |
| System Gates | — | 600K |
| Maximum User I/O (digchip) | — | 488 |
| Maximum User I/O (Altera) | — | 508 |
| Total Package Pins | — | 672 |
| Internal Performance | — | 301.21 MHz |
| Propagation Delay | — | 1.48 ns |
| Pin-Compatible With | — | APEX 20KE family |