EP2A15F672C9 vs EP2A15F672C9N 比較
詳細並排比較 EP2A15F672C9 由 Altera 與 EP2A15F672C9N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A15F672C9 | EP2A15F672C9N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Logic Family | APEX II (CMOS) | APEX II (CMOS) |
| Usable Gates | 600 K | — |
| Logic Elements | 16640 | — |
| Macrocells | 1664 | — |
| Maximum User I/Os | 492 | — |
| 封裝 | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine BGA) |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | — |
| Core Supply Voltage | 1.5 V | 1.5 V |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 379 MHz | — |
| Propagation Delay | 1.94 ns | 1.94 ns |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | — |
| Embedded Memory | ESB dual-port RAM / FIFO | Embedded dual-port RAM blocks |
| 工作溫度 | 0 °C to 85 °C (commercial) | 0°C to +85°C (commercial grade) |
| Configuration Interface | Passive serial / Active serial / JTAG (IEEE 1149.1) | — |
| PLLs | On-chip PLLs for clock synthesis and deskew | — |
| Compliance | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan | — |
| Series | — | Altera APEX II (EP2A) |
| Logic Elements / Cells | — | 16,640 |
| Equivalent Gates | — | 600,000 |
| Maximum User I/O Pins | — | 492 |
| Internal Operating Frequency (max) | — | 379 MHz |
| Technology Process | — | 0.15 µm all-layer copper CMOS, up to 8 metal layers |
| 安裝類型 | — | Surface Mount |
| MSL 等級 | — | 3 (per FC-FBGA moisture sensitivity, typical) |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |
| I/O Speed Grade | — | Up to 1 Gbps (LVDS) |
| Special Blocks | — | CAM (Content-Addressable Memory), dedicated multipliers, PLLs |
| Speed Grade | — | C9 (fastest commercial grade in the APEX II speed-grade system) |