EP2A40B724C7 vs EP2A40B724C7N 比較
詳細並排比較 EP2A40B724C7 由 Intel 與 EP2A40B724C7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A40B724C7 | EP2A40B724C7N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 38,400 | — |
| Total System Gates | 1,500,000 | — |
| Embedded RAM Bits | 655,360 | — |
| Maximum User I/O | 540 | — |
| Core Supply Voltage | 1.425 V to 1.575 V (typ. 1.5 V) | — |
| Process Technology | 0.15 µm CMOS, up to 8 metal layers, all-layer copper | 0.15 um CMOS |
| Maximum Internal Frequency | 562 MHz | — |
| PLLs | 4 | — |
| 封裝 | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm | 724-pin FCBGA (PBGA) |
| 工作溫度 | 0 °C to +85 °C (commercial) | — |
| I/O Standards Supported | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) | — |
| Configuration Method | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices | — |
| MultiVolt I/O Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V | — |
| DDR Memory Support | Yes (via ESB / I/O circuitry) | — |
| RoHS 狀態 | Non-compliant (lead-bearing FCBGA) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Series | — | EP2A40 |
| Device Type | — | FPGA (Loadable PLD) |
| System Gates | — | 1.5 M |
| Logic Cells / Elements | — | 38,400 |
| Maximum Internal Performance | — | 562 MHz |
| Propagation Delay | — | 1.55 ns |
| Core Supply Voltage (VCCINT) | — | 1.5 V nominal (1.425 V to 1.575 V) |
| User I/O Lines | — | 536 |
| JESD-30 Package Code | — | S-PBGA-B724 |
| Terminal Count | — | 724 |
| Output Function | — | MACROCELL |
| 工作溫度範圍 | — | 0 C to 85 C (commercial) |