EP2A40F1020C7N vs EP2A40F1020C9ES 比較

詳細並排比較 EP2A40F1020C7N 由 Intel 與 EP2A40F1020C9ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

Intel

EP2A40F1020C7N - APEX II 1.5M Gates FPGA, 735 I/O, FC-FBGA-1020 | Intel

EP2A40F1020C7N Obsolete

Altera

EP2A40F1020C9ES Obsolete

參數	EP2A40F1020C7N	EP2A40F1020C9ES
品牌	Intel	Altera
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	Obsolete	Obsolete
Family	APEX II	APEX II
Technology	0.15 µm all-layer copper CMOS, up to 8 metal layers	—
System Gates	1,500,000 (1.5 M)	1.5 M
Logic Elements	38,400	—
Embedded Memory	ESB-based, 504 Kbits total	Embedded System Blocks (ESBs) - RAM/ROM
Maximum Internal Performance	562 MHz	—
Propagation Delay	1.55 ns	—
User I/O Pins	735	—
PLLs	4	—
Clock Networks	12	—
True-LVDS Data Rate	1 Gbps	—
Supported I/O Standards	True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL	—
Core Supply Voltage	1.5 V nominal (1.425 V – 1.575 V)	1.5 V
Logic Family	CMOS	—
封裝	FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line	1020-pin FC-FBGA
工作溫度	0 °C to +85 °C (commercial, C7 grade)	[DATA_NEEDED: operating temperature grade]
Terminal Form	BGA ball (flip-chip)	—
安裝類型	Surface Mount	Surface Mount
Logic Cells / Elements	—	38,400
Maximum Internal Clock Frequency	—	366 MHz
Process Technology	—	0.15 µm CMOS
Package Type	—	Flip-Chip Fine-Pitch Ball Grid Array
I/O Standards	—	LVDS and other high-speed standards (per family datasheet)
RAM Support	—	Synchronous and asynchronous
RoHS 狀態	—	[DATA_NEEDED: RoHS status]
Lead-Free	—	[DATA_NEEDED: lead-free status]