EP2A40F672C7 vs EP2A40F672C6 比較

詳細並排比較 EP2A40F672C7 由 Intel 與 EP2A40F672C6 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A40F672C7 EP2A40F672C6
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX II APEX II
Logic Elements 38,400 —
System Gates 1,500,000 —
Macro Cells 2,560 —
Maximum User I/O 492 —
Process Technology 0.15 µm CMOS, all-layer copper, up to 8 metal layers 0.18-micron CMOS
Core Voltage 1.5 V —
I/O Voltage Support 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Pin-to-Pin Delay 1.55 ns (C7 speed grade) —
Maximum Internal Frequency 562 MHz —
High-Speed Interface 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport —
PLLs 4 —
封裝 672-ball FC-FBGA (FineLine BGA) 672-ball FineLine BGA (FBGA-672)
Package Dimensions 27 x 27 mm, 1.0 mm pitch —
安裝類型 Surface Mount Surface Mount (BGA)
Operating Temperature Grade Commercial (per 'C' suffix in speed grade) —
RoHS 狀態 Compliant [DATA_NEEDED: RoHS status]
Lead-Free Yes [DATA_NEEDED: lead-free status]
Device — EP2A40
Logic Elements (typical) — 40,000
Maximum System Gates — [DATA_NEEDED: maximum system gates]
Embedded System Blocks (ESBs) — [DATA_NEEDED: ESB count]
Maximum User I/O Pins — [DATA_NEEDED: max user I/O count]
Speed Grade — C6 (commercial)
工作溫度 — Commercial (0C to +85C)
Configuration Memory — SRAM-based
JTAG Support — Yes (IEEE 1149.1)
PLL Support — Yes
Lifecycle — Obsolete / EOL (per Intel/Altera product discontinuation notice)

資料表與資源

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