EP2A40F672C9 vs EP2A40F672C7 比較

詳細並排比較 EP2A40F672C9 由 Altera 與 EP2A40F672C7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP2A40F672C9 EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera

EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera

EP2A40F672C9 ⚠ 最後購買機會

規格比較

參數 EP2A40F672C9 EP2A40F672C7
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Family APEX II APEX II
Device Family APEX II PLD —
Logic Elements / Cells 38,400 —
System Gates 1.5 M 1,500,000
Macros 2,560 —
User I/Os 492 —
腳位數 672 —
封裝 672-BBGA, FC-FBGA (FineLine) 672-ball FC-FBGA (FineLine BGA)
Package Size 27 mm × 27 mm, 1 mm ball pitch —
Core Voltage 1.5 V 1.5 V
Process Technology 0.15 µm all-layer copper, up to 8 metal layers 0.15 µm CMOS, all-layer copper, up to 8 metal layers
Logic Family CMOS —
Propagation Delay 1.55 ns —
Internal Speed Grade 366 MHz —
工作溫度 0 °C to 85 °C (commercial) —
I/O Standards Supported True-LVDS, LVPECL, PCML, HyperTransport —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: RoHS status] Compliant
Logic Elements — 38,400
Macro Cells — 2,560
Maximum User I/O — 492
I/O Voltage Support — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
Pin-to-Pin Delay — 1.55 ns (C7 speed grade)
Maximum Internal Frequency — 562 MHz
High-Speed Interface — 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport
PLLs — 4
Package Dimensions — 27 x 27 mm, 1.0 mm pitch
Operating Temperature Grade — Commercial (per 'C' suffix in speed grade)
Lead-Free — Yes

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