EP2AGX125EF35C6G vs EP2AGX125EF35I5G 比較
詳細並排比較 EP2AGX125EF35C6G 由 Altera 與 EP2AGX125EF35I5G 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2AGX125EF35C6G | EP2AGX125EF35I5G |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Unknown | NRND |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Series | Arria II GX | Arria II GX |
| Number of Logic Elements/Cells | 118143 | — |
| Total RAM Bits | 8315904 bit | — |
| User I/O Pins | 452 | 452 |
| Core Supply Voltage | 0.87 V to 0.93 V | — |
| Number of LABs | [DATA_NEEDED: number of LABs] | — |
| 工作溫度 | 0 °C to 85 °C (Tj) | -40C to +100C (Industrial) |
| Package Type | 1152-BBGA, FCBGA | — |
| Supplier Device Package | 1152-FBGA (35 mm x 35 mm) | — |
| Package Pin Count | 1152 pin | — |
| 安裝類型 | [DATA_NEEDED: mounting type] | Surface Mount (BGA) |
| Maximum Operating Frequency | [DATA_NEEDED: maximum operating frequency] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Logic Elements | — | 118,143 |
| Embedded Memory | — | 8,315,904 bits (7.93 Mbits) |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| 封裝 | — | 1152-FBGA, FCBGA (35 mm) |
| Core Voltage | — | 0.87 V (Min) |
| Transceivers | — | 12 channels, up to 6.375 Gbps |
| PCIe Hard IP | — | 4 blocks, Gen1/Gen2 |
| PLLs | — | 8 |
| DSP Blocks | — | [DATA_NEEDED: DSP count] |
| Process Node | — | 40 nm low-power |
| Speed Grade | — | -5 |
| Total Memory Bits | — | 8,315,904 |