EP2AGZ225FF35C3G vs EP2AGZ225FF35C4G 比較
詳細並排比較 EP2AGZ225FF35C3G 由 Altera 與 EP2AGZ225FF35C4G 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2AGZ225FF35C3G | EP2AGZ225FF35C4G |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | Arria II GZ | — |
| Series | Arria II | — |
| Logic Elements (LE) | 225,000 | — |
| 封裝 | 1152-ball Flip-Chip BGA (FF35) | 1152FBGA |
| Package Size | 35 mm x 35 mm | — |
| 工作溫度 | 0C to +85C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Speed Grade | C3 | — |
| Transceivers | Up to 16 channels | [DATA_NEEDED: transceiver count] |
| Transceiver Data Rate (max) | 6.375 Gbps | — |
| DSP Blocks | [DATA_NEEDED: count] | [DATA_NEEDED: DSP block count] |
| Embedded Memory | [DATA_NEEDED: Mbits] | [DATA_NEEDED: embedded memory capacity] |
| User I/O Banks | [DATA_NEEDED: count] | — |
| Maximum User I/O | [DATA_NEEDED: pin count] | — |
| Process Technology | 40 nm TSMC | — |
| Memory Controller Support | DDR3, DDR2, QDR II+ | — |
| PCI Express Hard IP | Yes (Gen1/Gen2) | — |
| RoHS 狀態 | Compliant | unknown |
| 安裝類型 | Surface Mount (BGA) | — |
| MSL 等級 | 3 (per JEDEC J-STD-020) | — |
| Lead-Free | Yes | — |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Manufacturer | — | Intel |
| Product Family | — | FPGA |
| User I/O | — | 554 I/O |
| Package Type | — | Fine-pitch ball grid array |
| Logic Elements | — | [DATA_NEEDED: logic element count] |
| 供應電壓 | — | [DATA_NEEDED: supply voltage] |
| I/O Standards | — | [DATA_NEEDED: supported I/O standards] |
| Configuration Method | — | [DATA_NEEDED: configuration method] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | not_applicable |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |