EP2C50F672C7 vs EP2C35F672C7 比較
詳細並排比較 EP2C50F672C7 由 Altera 與 EP2C35F672C7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2C50F672C7 | EP2C35F672C7 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Family | Cyclone II | — |
| Logic Elements (LE) | 50,528 | 33,216 |
| Embedded Memory Bits | 594,432 bits | 483,840 bits (105 M4K blocks) |
| Embedded Memory Blocks | 250 M4K blocks (4 Kbit each) | — |
| Embedded 18x18 Multipliers | 86 (150 per device family datasheet figure) | 35 |
| User I/O Pins | 450 | — |
| Phase-Locked Loops (PLL) | 4 | — |
| Global Clock Networks | 16 | — |
| Process Technology | 90 nm CMOS with low-k dielectric | 90 nm low-k CMOS |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V (per bank) | — |
| 封裝 | 672-ball FineLine BGA (FBGA-672) | 672-BGA (FineLine BGA) |
| Speed Grade | -7 | 7 (commercial) |
| Temperature Grade | Commercial (0C to +85C junction) | — |
| Configuration Modes | Passive Serial (PS), Active Serial (AS), JTAG | — |
| Lead-Free / RoHS | Lead-Free / RoHS compliant per Heisener listing | — |
| Series | — | Cyclone II |
| User I/O Count | — | 475 |
| PLLs | — | 4 |
| Core Voltage | — | 1.2 V |
| 工作溫度 | — | 0C to +85C (commercial) |
| Configuration Interface | — | Serial (AS) and Parallel (PS) |
| Memory Interface Support | — | DDR, DDR2, QDRII SRAM |
| 安裝類型 | — | Surface Mount |
| RoHS 狀態 | — | Compliant |