EP2S130F1020C5N vs EP2S130F1020C3NRB 比較
詳細並排比較 EP2S130F1020C5N 由 Intel 與 EP2S130F1020C3NRB 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2S130F1020C5N | EP2S130F1020C3NRB |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | Stratix II | — |
| Logic Elements | 132,540 | — |
| Adaptive Logic Modules (ALMs) | 6627 LABs (per Jotrin listing) | — |
| Total Memory Bits | 6,747,840 bits | — |
| User I/Os | 734 | — |
| Process Technology | 90 nm | — |
| Core Supply Voltage (VCCINT) | 1.15 V to 1.25 V | — |
| Maximum Internal Frequency | 609.76 MHz | — |
| 封裝 | 1020-ball FC-FBGA (33x33 mm) | 1020-BBGA (33x33 mm, 1.0 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | Commercial (0C to +85C, C5 grade) | 0C to +85C (commercial, C3 speed grade) |
| Temperature Grade | C5 (other - per Partstack) | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| PLLs | 4 (typical Stratix II feature) | — |
| Global Clock Networks | 16 (typical Stratix II feature) | — |
| Configuration Method | Serial/Parallel via Quartus II (typical Stratix II) | — |
| Country of Origin | Republic of Korea (per GlobalSpec) | — |
| ECCN | 3A001.a.7.a (per GlobalSpec) | — |
| Estimated EOL Date | 2023 (per GlobalSpec) | — |
| Manufacturer | — | Intel Corporation (formerly Altera) |
| Series | — | Stratix II |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements (LEs) | — | 132,540 |
| Total Memory | — | 6,748 Kbits |
| LABs/CLBs | — | 6,627 |
| User I/O Count | — | 742 |
| Process Node | — | 90 nm |
| Lead Free / RoHS Status | — | Lead Free / RoHS Compliant |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |
| Voltage - Supply (VCCINT) | — | [DATA_NEEDED: VCCINT nominal] |
| Voltage - I/O Banks | — | [DATA_NEEDED: VCCIO range] |