EP2S30F672C3 vs EP2S30F672C4 比較

詳細並排比較 EP2S30F672C3 由 Intel 與 EP2S30F672C4 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2S30F672C3 EP2S30F672C4
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Series Stratix II Stratix II
Number of Logic Elements 33,880 —
Number of Adaptive Logic Modules (ALMs) 13,560 —
Total Embedded Memory Bits 1,369,728 —
Embedded Memory (M512 / M4K / M-RAM blocks) M512, M4K, M-RAM TriMatrix —
Total RAM Bits 1,369,728 1,369,728
Number of User I/O 500 —
Number of Transceivers [DATA_NEEDED: depends on variant - up to 12] —
DSP Blocks Dedicated 18x18 multipliers —
DSP Performance Up to 156 GMACs —
Voltage - Supply 1.2 V core, multi-rail I/O —
工作溫度 0C to +85C (Commercial) 0C to +85C (commercial, 'C' speed grade)
Speed Grade -3 —
封裝 / 外殼 672-BBGA, FCBGA (FineLine BGA) —
安裝類型 Surface Mount Surface Mount
Process Technology 90 nm CMOS 90 nm
RoHS 狀態 Non-compliant (leaded BGA) Compliant
MSL 等級 [DATA_NEEDED: MSL rating] —
Manufacturer — Intel (formerly Altera)
Logic Elements / Cells — 33,880
Number of I/O — 500
封裝 — 672-BBGA, FCBGA (27x27 mm)
Core Voltage - Supply — 1.15 V to 1.25 V
Maximum Core Frequency (datasheet benchmark) — 711 MHz
Embedded DSP Blocks — 16 (Stratix II S30 tier)
Number of PLLs — [DATA_NEEDED: PLL count for S30 tier]
Number of Global Clock Networks — [DATA_NEEDED: global clock network count]
Lead-Free — Yes

資料表與資源

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