EP2S60F1020C5 vs EP2S130F1020C5N 比較

詳細並排比較 EP2S60F1020C5 由 Intel 與 EP2S130F1020C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2S60F1020C5 EP2S130F1020C5N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND NRND
Family Stratix II Stratix II
Logic Elements 60,440 132,540
Adaptive Logic Modules (ALMs) 30,220 6627 LABs (per Jotrin listing)
Equivalent Logic Elements 60,440 —
Total RAM Bits 2,544,192 —
DSP Blocks 256 (18x18 multipliers) —
Maximum User I/O 718 —
Embedded Transceivers 12 (up to 6.375 Gbps) —
PLLs 4 4 (typical Stratix II feature)
Global Clock Networks 16 16 (typical Stratix II feature)
封裝 1020-ball FC-FBGA (33x33 mm, 1.0 mm pitch) 1020-ball FC-FBGA (33x33 mm)
Speed Grade C5 (commercial) —
Temperature Grade Commercial (0C to +85C) C5 (other - per Partstack)
Process Technology 90 nm CMOS 90 nm
Core Voltage 1.2 V —
安裝類型 Surface Mount (BGA) Surface Mount
MSL 等級 [DATA_NEEDED: MSL level] —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs status]
Total Memory Bits — 6,747,840 bits
User I/Os — 734
Core Supply Voltage (VCCINT) — 1.15 V to 1.25 V
Maximum Internal Frequency — 609.76 MHz
工作溫度 — Commercial (0C to +85C, C5 grade)
Lead-Free — [DATA_NEEDED: lead-free status]
Configuration Method — Serial/Parallel via Quartus II (typical Stratix II)
Country of Origin — Republic of Korea (per GlobalSpec)
ECCN — 3A001.a.7.a (per GlobalSpec)
Estimated EOL Date — 2023 (per GlobalSpec)

資料表與資源

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