EP2S60F1020I4 vs EP2S60F1020I4N 比較
詳細並排比較 EP2S60F1020I4 由 Altera 與 EP2S60F1020I4N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2S60F1020I4 | EP2S60F1020I4N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Manufacturer | Intel / Altera | — |
| Series | Stratix II | Stratix II |
| Logic Elements (LEs) | 60,440 | — |
| Embedded Memory (bits) | 2,544,192 | — |
| Number of LABs/CLBs | 3022 | — |
| Number of CLBs | 24176 | — |
| Maximum User I/O | 718 | 718 |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | 32 |
| Operating Voltage (Core) | 1.2 V | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Temperature Grade | Industrial (-40C to +100C TJ) | — |
| Package Type | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) | — |
| Package Dimensions | 33 mm x 33 mm | — |
| Ball Pitch | 1.0 mm | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| Configuration Method | Passive Serial / Fast Passive Parallel / JTAG | — |
| Number of PLLs | 12 | — |
| Global Clock Networks | 16 | — |
| Embedded Multipliers (18x18) | 36 | — |
| Transceiver Count | 0 (no embedded transceivers) | — |
| Maximum Embedded Memory Bandwidth | [DATA_NEEDED: memory bandwidth spec] | — |
| RoHS 狀態 | Non-compliant (contains lead per legacy Altera package) | unknown |
| Family | — | Stratix II FPGA |
| Logic Elements (LE) | — | 60,440 |
| Embedded Memory Bits | — | 2,544,192 |
| DSP Blocks (18x18 multipliers) | — | 36 |
| PLLs | — | 12 |
| Core Voltage | — | 1.2 V |
| 封裝 | — | 1020-ball FCBGA (33 x 33 mm) |
| 工作溫度 | — | -40C to +100C (Industrial) |
| Speed Grade | — | -4 |
| Configuration Scheme | — | PS, PPS, PPA, FPP, JTAG |
| Embedded Transceiver Channels | — | 12 channels up to 6.375 Gbps |