EP3SE50F780C4 vs EP3SE50F780C4N 比較

詳細並排比較 EP3SE50F780C4 由 Altera 與 EP3SE50F780C4N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP3SE50F780C4 EP3SE50F780C4N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 NRND
Family Stratix III E Stratix III E
Logic Elements (LE) 47,500 47,500
Embedded Memory (bits) 5,760,000 —
Maximum User I/O 488 —
Logic Array Blocks (LABs) 1,900 —
Maximum Internal Frequency 800 MHz —
Process Technology 65 nm —
Core Supply Voltage 1.1 V —
Speed Grade C4 (commercial) —
工作溫度 0C to +85C 0C to +85C (C4 commercial grade)
封裝 780-Ball FC-FBGA (BBGA) 780-Ball FBGA, 29 mm x 29 mm, 1.0 mm pitch
安裝類型 Surface Mount Surface Mount (BGA)
RoHS 狀態 [DATA_NEEDED: rohs_status] Lead-free / RoHS compliant
MSL 等級 [DATA_NEEDED: msl_level] 3 (per JEDEC J-STD-020, FBGA package)
Transceivers [DATA_NEEDED: transceiver_count_and_rate] —
Embedded Memory Bits — 5,760,000
Embedded Memory (M9K/M144K blocks) — 488 (per family datasheet)
Number of LABs — 1900
Maximum User I/Os — 488
DSP Blocks (18x18 multipliers) — 432
PLLs — 12 (per family datasheet)
Maximum Operating Frequency — 717 MHz
Transceiver Channels — Up to 12 (per family, model-dependent)
Transceiver Data Rate — Up to 6.375 Gbps (per Stratix III E family)
Process Node — 40 nm
供應電壓 — Core 0.9 V, I/O 1.2 V-3.3 V (multi-rail)
Configuration Modes — JTAG, Passive Serial, Fast Passive Parallel
Hard Memory Controller — DDR2/DDR3 SDRAM (per Stratix III E family)

資料表與資源

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