EP3SL50F484I4L vs EP3SL50F484I4 比較
詳細並排比較 EP3SL50F484I4L 由 Intel 與 EP3SL50F484I4 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP3SL50F484I4L | EP3SL50F484I4 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Series | Stratix III L (Low Power) | — |
| Family | Stratix III | — |
| Logic Elements (LE) | 47,500 | 47,500 |
| Embedded Memory Bits | 2,184,192 bits (~273 KB) | 2,184,192 bits |
| User I/O Pins | 296 | — |
| 封裝 | 484-ball FBGA (FCBGA) | 484-ball FC-FBGA (FCBGA, 1.0 mm pitch) |
| Speed Grade | 4 | — |
| 工作溫度 | 0 °C to 85 °C (commercial, per DigiKey listing) | -40C to +100C (industrial) |
| 供應電壓 | 0.9 V core (family-typical) | — |
| Process Technology | 65 nm low-power CMOS | 65 nm CMOS |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| Lead-Free / RoHS | Yes (RoHS compliant) | — |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | JTAG, Passive Serial, FPP, PPA |
| Transceivers | Family supports up to 4 transceivers per family datasheet | — |
| DSP Blocks | Family supports up to 384 18x18 multipliers (family-level) | — |
| Device Family | — | Stratix III L |
| Logic Array Blocks (LABs) | — | 1,900 |
| Maximum User I/O | — | 296 |
| Internal Frequency | — | 800 MHz (max, per digchip datasheet summary) |
| Core Supply Voltage | — | 1.1 V |
| Grade Suffix | — | I4 = Industrial, speed grade 4 |
| MultiTrack Interconnect | — | Yes |
| TriMatrix Embedded Memory | — | MLAB, M9K, M144K blocks |
| MSL 等級 | — | 3 (168 hours) |
| RoHS 狀態 | — | Compliant |
| Lead-Free | — | Yes |