EP610DC-30 vs EP610DC15 比較
詳細並排比較 EP610DC-30 由 Altera 與 EP610DC15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DC-30 | EP610DC15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | EP610 (Classic Device Family) | EP610 Classic EPLD |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 15 ns |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | — |
| 封裝 | 24-pin CERDIP (windowed) | 24-pin CDIP (Ceramic DIP, windowed) |
| 安裝類型 | Through-Hole | Through-Hole |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | CMOS |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| 工作溫度 | Commercial (0C to +70C) | 0C to +70C |
| Architecture | — | PAL-type |
| Maximum Clock Frequency (fMAX) | — | 71.4 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Total Inputs | — | 20 |
| I/O Lines | — | 16 |
| Product Terms | — | 160 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Reprogrammability | — | Yes (UV erasable via windowed package) |
| RoHS 狀態 | — | unknown |