EP610DC15 vs EP610DI-35 比較
詳細並排比較 EP610DC15 由 Intel 與 EP610DI-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 Obsolete規格比較
| 參數 | EP610DC15 | EP610DI-35 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 Classic EPLD | Altera Classic EPLD |
| Macrocells | 16 | — |
| Architecture | PAL-type | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 71.4 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Total Inputs | 20 | 20 (including 4 dedicated inputs) |
| I/O Lines | 16 | — |
| Product Terms | 160 | 160 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | CMOS | CMOS, UV-erasable |
| 工作溫度 | 0C to +70C | [DATA_NEEDED: industrial/commercial grade range] |
| 封裝 | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CDIP (Ceramic DIP) |
| 安裝類型 | Through-Hole | Through-hole |
| Reprogrammability | Yes (UV erasable via windowed package) | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: not confirmed in supplied web data] |
| Series | — | EP610 |
| Logic Cells / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 |
| I/O Pins | — | 16 bidirectional |
| Propagation Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Internal Pipelined Data Rate | — | Up to 100 MHz |
| 供應電壓 | — | 5 V |