EP610ILC-10 vs EP610ILC10 比較
詳細並排比較 EP610ILC-10 由 Altera 與 EP610ILC10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610ILC-10 | EP610ILC10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | — |
| Architecture | PAL-type with macrocells | PAL-type AND-OR-NOT |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Product Terms | 160 | 160 |
| I/O Pins | 16 | — |
| Dedicated Inputs | 4 | 4 |
| 供應電壓 | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| 封裝 | PLCC-28 (plastic J-lead chip carrier) | 28-pin PLCC (J-Lead) |
| 安裝類型 | Surface Mount (PLCC socket or solder) | Surface Mount / Socket |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (Industrial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Unknown - verify with manufacturer |
| Family | — | Classic EPLD (EP610) |
| Logic Elements | — | 16 macrocells |
| Gates | — | 300 gates equivalent |
| I/O Lines | — | 16 |
| Propagation Delay (tPD) | — | 15 ns (10 ns speed grade) |
| Maximum Internal Frequency | — | 100 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS, UV-erasable / OTP |