EP610ILC-25 vs EP610ILC-10 比較
詳細並排比較 EP610ILC-25 由 Altera 與 EP610ILC-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610ILC-25 | EP610ILC-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP610 series) | — |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | 300 |
| Macrocells | 16 | 16 |
| Product Terms | 160 | 160 |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | 4 |
| Bidirectional I/O Pins | 16 | — |
| 工作溫度範圍 | 0 C to +70 C (commercial) | — |
| 封裝 | 28-pin PLCC (J-lead) | PLCC-28 (plastic J-lead chip carrier) |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket or solder) |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | Classic EPLD |
| Product Type | — | UV-Erasable / OTP PLD |
| Architecture | — | PAL-type with macrocells |
| I/O Pins | — | 16 |
| 供應電壓 | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |