EP610JI-30 vs EP610LI-30 比較
詳細並排比較 EP610JI-30 由 Altera 與 EP610LI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610JI-30 | EP610LI-30 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Family | Altera Classic EPLD (EP610) | Classic EPLD (MAX architecture) |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tpd) | 30 ns (max) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Product Terms | 160 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| External Clocks | 2 | — |
| 供應電壓 | 5 V (single supply) | — |
| Process Technology | CMOS | CMOS, UV-erasable EPROM cells |
| 封裝 | CQCC28 (windowed ceramic JLCC, J-bend) | 24-pin Ceramic DIP (windowed, CDIP) |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| 工作溫度 | -40C to +85C (industrial, per EP610 family suffix convention) | -55C to +125C (military/extended) |
| 安裝類型 | Surface Mount (JLCC) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Maximum Internal Frequency (fMAX) | — | 100 MHz (pipelined) |
| AND Array | — | 24V16 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible I/O) |
| Output Polarity | — | User-configurable per macrocell |
| Flip-Flop per Cell | — | D / T / J-K configurable |
| Programming Method | — | UV erase + Classic-series PLD programmer |
| Manufacturer | — | Rochester Electronics (originally Altera) |