EP610JI-30 vs EP610PI-30 比較
詳細並排比較 EP610JI-30 由 Altera 與 EP610PI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610JI-30 | EP610PI-30 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | Altera Classic EPLD (EP610) | EP610 Classic EPLD |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 16 | — |
| Propagation Delay (tpd) | 30 ns (max) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Product Terms | 160 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| External Clocks | 2 | — |
| 供應電壓 | 5 V (single supply) | — |
| Process Technology | CMOS | CMOS EEPROM |
| 封裝 | CQCC28 (windowed ceramic JLCC, J-bend) | PDIP-24 (Plastic DIP) |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| 工作溫度 | -40C to +85C (industrial, per EP610 family suffix convention) | [DATA_NEEDED: operating temperature range] |
| 安裝類型 | Surface Mount (JLCC) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | Not Compliant (per distributor data) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 gates |
| Propagation Delay (tPD) | — | 30 ns (PI-30 speed grade) |
| Maximum Frequency (pipelined) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5 V |
| 腳位數 | — | 24 |
| Number of Global Clocks | — | 2 |
| Number of Dedicated Inputs | — | 4 |
| Number of I/O Pins | — | 10 |
| Programming Technology | — | EEPROM (in-system, 100+ cycles) |
| ECCN | — | EAR99 |
| HTS Code | — | 8542.39.00.01 |