EP610LI-30 vs EP610LI-35 比較
詳細並排比較 EP610LI-30 由 Rochester Electronics 與 EP610LI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610LI-30 | EP610LI-35 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD (MAX architecture) | Classic EPLD |
| Macrocells | 16 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Maximum Internal Frequency (fMAX) | 100 MHz (pipelined) | — |
| AND Array | 24V16 | — |
| Process Technology | CMOS, UV-erasable EPROM cells | CMOS |
| Supply Voltage (VCC) | 5 V (TTL-compatible I/O) | — |
| 封裝 | 24-pin Ceramic DIP (windowed, CDIP) | 28-pin PLCC (windowed ceramic, 'LI') |
| 工作溫度 | -55C to +125C (military/extended) | — |
| Output Polarity | User-configurable per macrocell | — |
| Flip-Flop per Cell | D / T / J-K configurable | — |
| Programming Method | UV erase + Classic-series PLD programmer | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | Rochester Electronics (originally Altera) | — |
| Series | — | EP610 |
| Number of Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Number of I/O Pins | — | 16 |
| Total Inputs | — | 20 |
| Dedicated Inputs | — | 4 |
| External Clock Inputs | — | 2 |
| Product Terms | — | 160 |
| Maximum Propagation Delay | — | 35 ns (tpd) |
| Maximum Operating Frequency | — | 28.6 MHz (fmax) |
| Pipelined Data Rate | — | Up to 100 MHz |
| 供應電壓 | — | 5 V |
| Architecture | — | PAL-type (AND-OR array) |
| 工作溫度範圍 | — | [DATA_NEEDED: military/industrial operating temperature range] |
| Programming Technology | — | UV-erasable (EPROM) |
| 安裝類型 | — | Surface Mount |