EP610PC-20T vs EP610PC-30 比較
詳細並排比較 EP610PC-20T 由 Intel 與 EP610PC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-20T | EP610PC-30 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | Classic EPLD | — |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | 300 |
| Propagation Delay (tPD) | 20 ns | 30 ns |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| Number of Dedicated Inputs | 16 | — |
| Number of I/O Pins | 16 | — |
| Programmable Output Enable | Yes (per macrocell) | — |
| 封裝 | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (0.300 inch) |
| 安裝類型 | Through-Hole | Through-Hole |
| 工作溫度 | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM, CMOS | — |
| Development Tool | MAX+PLUS II | — |
| RoHS 狀態 | unknown | Not applicable (legacy non-compliant package per distributor listing) |
| Device Family | — | Classic EPLD (EP610) |
| Macrocells | — | 16 |
| Maximum Pipeline Frequency | — | 33.3 MHz (typical) / 100 MHz pipelined |
| Process Technology | — | CMOS EPROM |
| Programmability | — | One-Time Programmable (OTP, no window on plastic PDIP) |
| Output Drive Current | — | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] |
| Input Pins (Dedicated) | — | [DATA_NEEDED: dedicated input count from datasheet pinout] |
| I/O Pins | — | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] |
| Programming Tool | — | Altera A+PLUS / MAX+PLUS II (legacy) |
| Lead Free Status | — | Not applicable |
| Current Distributor | — | Rochester Electronics, LLC (authorized continuing source) |