EP610PC-25 vs EP610PC-20 比較
詳細並排比較 EP610PC-25 由 Altera 與 EP610PC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-25 | EP610PC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP610 series) | — |
| Macro Cells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Technology | CMOS, EPROM (UV-erasable) | — |
| Device Type | OT PLD, PAL-type, CMOS | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 (bidirectional, JTAG-programmable OE per macrocell) | — |
| 封裝 | PDIP-24 (0.3 inch, through-hole) | PDIP-24 |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Programming Method | EPROM (UV-erasable), via Altera programming hardware | — |
| 安裝類型 | Through-Hole (DIP) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-compliant (legacy PDIP) |
| Family | — | Classic EPLD |
| Logic Elements | — | 16 macrocells |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz (pipelined) |
| Supply Voltage (VCC) | — | 5 V ±10% |
| 腳位數 | — | 24 |
| Process Technology | — | CMOS EPROM |
| Programmable Flip-Flops | — | 16 |
| Input Pins | — | 24 |
| Output Pins | — | 16 |
| I/O Compatibility | — | TTL |
| Program/Erase Method | — | UV (windowed) or OTP |