EP610PC-25T vs EP610PC-30 比較

詳細並排比較 EP610PC-25T 由 Intel 與 EP610PC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP610PC-25T EP610PC-30
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 NRND
Manufacturer Intel (formerly Altera) —
Distributor / Stocking Source Rochester Electronics, LLC —
Device Family Altera Classic EPLD - EP610 Classic EPLD (EP610)
Device Type Erasable Programmable Logic Device (EPLD, OTP for plastic package) —
Logic Capacity 300 usable gates —
Macro Cells 16 —
Registers 16 —
User I/Os 16 —
Propagation Delay (tPD) 25 ns (speed grade 25) 30 ns
Maximum Toggle Frequency [DATA_NEEDED: max fmax] —
Pipelined Data Rate up to 100 MHz —
Supply Voltage (VCC) 5 V 5 V (4.75 V to 5.25 V)
Process Technology ECMOS (CMOS, EPROM-based) CMOS EPROM
封裝 PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) 24-pin PDIP (0.300 inch)
Pinout Compatibility Pin-compatible with EP610DC-25 (CERDIP-24, windowed) —
工作溫度 0 °C to +70 °C (commercial) 0C to +70C (commercial)
Programming Method OTP (one-time programmable) via Altera programming hardware —
安裝類型 Through-hole Through-Hole
RoHS 狀態 [DATA_NEEDED: RoHS status] Not applicable (legacy non-compliant package per distributor listing)
Shipping Form (T suffix) Tube —
Macrocells — 16
Usable Gates — 300
Maximum Pipeline Frequency — 33.3 MHz (typical) / 100 MHz pipelined
Programmability — One-Time Programmable (OTP, no window on plastic PDIP)
Output Drive Current — [DATA_NEEDED: IOH/IOL per datasheet DC characteristics]
Input Pins (Dedicated) — [DATA_NEEDED: dedicated input count from datasheet pinout]
I/O Pins — [DATA_NEEDED: bidirectional I/O count from datasheet pinout]
Programming Tool — Altera A+PLUS / MAX+PLUS II (legacy)
Lead Free Status — Not applicable
Current Distributor — Rochester Electronics, LLC (authorized continuing source)

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