EP610PC25 vs EP610PC-30 比較
詳細並排比較 EP610PC25 由 Altera 與 EP610PC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC25 | EP610PC-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | Altera Classic EPLD | Classic EPLD (EP610) |
| Logic Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 25 ns | 30 ns |
| Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | 12 V | — |
| ICC (typical) | 200 mA | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| 封裝 | PDIP-24 | 24-pin PDIP (0.300 inch) |
| 安裝類型 | Through-Hole | Through-Hole |
| Programmability | One-Time-Programmable (OTP), UV-erasable variant exists | One-Time Programmable (OTP, no window on plastic PDIP) |
| 腳位數 | 24 | — |
| Technology | 5 V CMOS | — |
| RoHS 狀態 | unknown | Not applicable (legacy non-compliant package per distributor listing) |
| Lifecycle | Obsolete (last shipped ~2000s) | — |
| Maximum Pipeline Frequency | — | 33.3 MHz (typical) / 100 MHz pipelined |
| Process Technology | — | CMOS EPROM |
| Output Drive Current | — | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] |
| Input Pins (Dedicated) | — | [DATA_NEEDED: dedicated input count from datasheet pinout] |
| I/O Pins | — | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] |
| Programming Tool | — | Altera A+PLUS / MAX+PLUS II (legacy) |
| Lead Free Status | — | Not applicable |
| Current Distributor | — | Rochester Electronics, LLC (authorized continuing source) |