EP910DC-40 vs EP910DI-30 比較
詳細並排比較 EP910DC-40 由 Altera 與 EP910DI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 Nrnd規格比較
| 參數 | EP910DC-40 | EP910DI-30 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| 供應電壓 | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| 封裝 | DIP-40 (ceramic, through-hole) | CDIP-40 (ceramic DIP, 40-pin with UV window) |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| RoHS 狀態 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Product Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Family | — | Classic EPLD (Altera EP910 series) |
| Macrocell Count | — | 24 |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Toggle Frequency (fmax) | — | 62 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Technology | — | CMOS, UV-erasable EPROM |
| Dedicated I/O Pins | — | 12 (12 input + 12 output) |
| Output Enable Pins | — | 2 |
| 腳位數 | — | 40 |
| Programmable Logic Element | — | JEDEC fuse map (3rd-party programmer) |
| 工作溫度 | — | -40C to +85C (industrial) |
| Manufacturer (Original) | — | Altera (now Intel PSG) |
| Current Distributor / Authorized Aftermarket | — | Rochester Electronics, LLC |