EP910ILC-12 vs EP910LI-35 比較
詳細並排比較 EP910ILC-12 由 Intel 與 EP910LI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910ILC-12 | EP910LI-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera EP910 Classic EPLD | Altera Classic EPLD |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 (typical) | 900 |
| Propagation Delay (tPD) | 12 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply | 5 V | — |
| Memory Technology | UV-erasable CMOS EPROM | — |
| 封裝 | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | 44-pin PLCC (J-lead) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | -40 °C to +85 °C (industrial grade, 'I' suffix) | -40 °C to +85 °C (Industrial) |
| Configuration Storage | Non-volatile EPROM (instant-on) | — |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| 腳位數 | 28 | — |
| Feedback Paths | 16 dedicated | — |
| Device Series | — | EP910 |
| Macrocells | — | 24 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| 供應電壓 | — | 5 V (4.75 V to 5.25 V) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Lead Pitch | — | 1.27 mm |