EP910ILC-15N vs EP910ILC-15 比較
詳細並排比較 EP910ILC-15N 由 Altera 與 EP910ILC-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete規格比較
| 參數 | EP910ILC-15N | EP910ILC-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic | Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 | 450 |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 66.6 MHz | 83.33 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O Pins | 36 | 36 |
| Dedicated Input Pins | 16 | — |
| 封裝 | PLCC-44 (J-lead, surface mount) | 44-pin PLCC (J-lead) |
| 安裝類型 | Surface Mount | Surface Mount (SMT) |
| 工作溫度 | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Series | — | EP910 |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 15 ns |
| 供應電壓 | — | 5 V |
| 記憶體類型 | — | EPROM (UV-erasable) |
| Propagation Class | — | -15 speed grade |
| Storage Condition | — | Dry cabinet, humidity-controlled |